High-speed interface integrated circuits (ICs), such as HDMI (High Definition Multimedia Interface) and USB-3, require high levels of electrostatic discharge (ESD) protection to interface safely with cables and connectors. Diode-based ESD protection devices, such as dual-diode protection circuits or diode-isolated snapback devices are the only ESD solutions that can be optimized on an IC in the sub-1 pF range to meet many of the speed and ESD requirements of the interface ICs.
There are advantages to using diodes with lightly doped regions for ESD protection. However, these diodes are often associated with high voltage overshoots during fast transient events resulting from ESD events. The high voltage overshoots are primarily due to the time it takes carriers to establish conductivity modulation. It is known that the voltage overshoot of the ESD protection devices can damage the gate oxides of protected MOS transistors; however, these devices had not suffered failures of the forward-biased ESD diodes due to the voltage overshoot until recently. These failures are caused by current filamentation in the diodes due to the voltage overshoots.
The voltage overshoots are dependent on the voltage drop across the diodes during ESD events. Therefore, the diodes must have low voltage drops during ESD events and have low parasitic capacitance. The development cycle for designing such diodes for high-speed ESD protections is often expensive because these parameters cannot be modeled, so the design involves multiple steps of IC fabrication. More specifically, the diodes are fabricated in silicon or another semiconductor material and their parameters are measured after fabrication, which is time consuming and expensive. If the diode parameters show a high voltage overshoot or a high capacitance, the diode parameters are changed and a new diode is fabricated and measured. The process continues until a satisfactory diode is achieved.